A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Era

Due to several physical limitations in the realization of quantum hardware, today’s quantum computers are qualified as noisy intermediate-scale quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current realizations of superconducting quantum chips do not have the ideal all-to-all connectivity between […]

Logical Clifford Synthesis for Stabilizer Codes

Quantum error-correcting codes are used to protect qubits involved in quantum computation. This process requires logical operators to be translated into physical operators acting on physical quantum states. In this article, we propose a mathematical framework for synthesizing physical circuits that implement logical Clifford operators for stabilizer codes. Circuit synthesis is enabled by representing the […]

Experimental Characterization, Modeling, and Analysis of Crosstalk in a Quantum Computer

In this article, we present the experimental characterization of crosstalk in quantum information processor using idle tomography and simultaneous randomized benchmarking. We quantify both “quantum” and “classical” crosstalk in the device and analyze quantum circuits considering crosstalk. We show that simulation considering only gate-error deviates from experimental results up to 27%, whereas simulation considering both […]

Subdivided Phase Oracle for NISQ Search Algorithms

Because noisy intermediate-scale quantum (NISQ) machines accumulate errors quickly, we need new approaches to designing NISQ-aware algorithms and assessing their performance. Algorithms with characteristics that appear less desirable under ideal circumstances, such as lower success probability, may in fact outperform their ideal counterparts on existing hardware. We propose an adaptation of Grover’s algorithm, subdividing the […]

Quantum Computer Architecture Toward Full-Stack Quantum Accelerators

This article presents the definition and implementation of a quantum computer architecture to enable creating a new computational device-a quantum computer as an accelerator. A key question addressed is what such a quantum computer is and how it relates to the classical processor that controls the entire execution process. In this article, we present explicitly […]

Enhancing a Near-Term Quantum Accelerator’s Instruction Set Architecture for Materials Science Applications

Quantum computers with tens to hundreds of noisy qubits are being developed today. To be useful for real-world applications, we believe that these near-term systems cannot simply be scaled-down non-error-corrected versions of future fault-tolerant large-scale quantum computers. These near-term systems require specific architecture and design attributes to realize their full potential. To efficiently execute an […]

Fault-Tolerant Resource Estimation of Quantum Random-Access Memories

Quantum random-access lookup of a string of classical bits is a necessary ingredient in several important quantum algorithms. In some cases, the cost of such quantum random-access memory (qRAM) is the limiting factor in the implementation of the algorithm. In this article, we study the cost of fault-tolerantly implementing a qRAM. We construct and analyze […]

Reducing the Cost of Implementing the Advanced Encryption Standard as a Quantum Circuit

To quantify security levels in a postquantum scenario, it is common to use the quantum resources needed to attack the Advanced Encryption Standard (AES) as a reference value. Specifically, in the National Institute of Standards and Technology’s ongoing postquantum standardization effort, different security categories are defined that reflect the quantum resources needed to attack AES-128, […]