Logic gates Archives - IEEE Transactions on Quantum Engineering

Multiplexed Bilayered Realization of Fault-Tolerant Quantum Computation Over Optically Networked Trapped-Ion Modules

January 12, 2026Nitish Kumar Chandra Saikat Guha Kaushik P. SeshadreesanQuantum Computing, UncategorizedComputer architecture, Fault tolerance, Fault tolerant systems, Lattices, Logic gates, Noise, Optical variables measurement, Particle beam optics, Qubit, Trapped ions

Abstract: We study an architecture for fault-tolerant measurement-based quantum computation (FT-MBQC) over optically-networked trapped-ion modules. The architecture is implemented with a finite number of modules and ions per module, and leverages photonic interactions for generating remote entanglement between modules and local Coulomb interactions for intra-modular entangling gates. We focus on generating the topologically protected Raussendorf–Harrington–Goyal […]

Exploration of Design Alternatives for Reducing Idle Time in Shor’s Algorithm: A Study on Monolithic and Distributed Quantum Systems

September 17, 2025Moritz Schmidt Abhoy Kole Leon Wichette Rolf Drechsler Frank Kirchner Elie MounzerQuantum Computing, UncategorizedArithmetic, Computer architecture, Hardware, Logic gates, Optimization, Quantum circuit, Quantum computing, Qubit, Registers, Standards

Abstract: Shor’s algorithm is one of the most prominent quantum algorithms, yet finding efficient implementations remains an active research challenge. While many approaches focus on low-level modular arithmetic optimizations, a broader perspective can provide additional opportunities for improvement. By adopting a midlevel abstraction, we analyze the algorithm as a sequence of computational tasks, enabling systematic […]

Benchmarking the Ability of a Controller to Execute Quantum Error Corrected Non-Clifford Circuits

September 9, 2025Yaniv Kurman Lior Ella Ramon Szmuk Oded Wertheim Benedikt Dorschner Sam StanwyckEnabling TechnologiesBenchmark testing, Circuits, Codes, Decoding, Fault tolerance, Fault tolerant systems, Logic gates, Measurement uncertainty, Quantum computing, Qubit

Abstract: Reaching fault-tolerant quantum computation relies on the successful implementation of non-Clifford circuits with quantum error correction (QEC). In QEC, quantum gates and measurements encode quantum information into an error-protected Hilbert space, while classical processing decodes the measurements into logical errors. QEC non-Clifford gates pose the greatest computation challenge from the classical controller’s perspective, as […]

A Grover-Meets-Simon Approach to Match Vector Boolean Functions

August 4, 2025Marco Venere; Alessandro Barenghi; Gerardo PelosiQuantum ComputingBenchmark testing, Boolean functions, Digital circuits, Integrated circuit interconnections, Libraries, Logic gates, Polynomials, Quantum algorithm, Time complexity, Vectors

Abstract: The Boolean matching problem via NP-equivalence requires determining whether two Boolean functions are equivalent or not up to a permutation and negation of the input binary variables. Its solution is a fundamental step in the electronic design automation (EDA) tool chains commonly used for digital circuit design. In fact, the library-mapping step of an […]

Simulation of Shor Algorithm for Discrete Logarithm Problems With Comprehensive Pairs of Modulo p and Order q

July 21, 2025Kaito Kishi; Junpei Yamaguchi; Tetsuya Izu; Noboru KunihiroQuantum InformationComputers, Cryptography, Fourier transforms, Logic gates, Noise measurement, Quantum algorithm, Quantum circuit, Quantum computing, Qubit, Registers

Abstract: The discrete logarithm problem (DLP) over finite fields, commonly used in classical cryptography, has no known polynomial-time algorithm on classical computers. However, Shor has provided its polynomial-time algorithm on quantum computers. Nevertheless, there are only few examples simulating quantum circuits that operate on general pairs of modulo p and order q. In this article, […]

SU(4) Gate Design via Unitary Process Tomography: Its Application to Cross-Resonance-Based Superconducting Quantum Devices

July 3, 2025Michihiko Sugawara; Takahiko SatohPhysical ImplementationsCalibration, Coherence time, Logic gates, Qubit, Resonance, Schedules, Superconducting microwave devices, Systematics, Tensors, Tomography

Abstract: In this article, we present a novel approach for implementing pulse-efficient SU(4) gates on cross resonance (CR)-based superconducting quantum devices. Our method introduces a parameterized unitary derived from the CR-Hamiltonian propagator, which accounts for ZZ-interactions. Leveraging the Weyl chamber’s geometric structure, we successfully realize a continuous two-qubit basis gate, RZZ(θ), as an echo-free pulse […]

Cryo-CMOS Bias-Voltage Generation and Demultiplexing at mK Temperatures for Large-Scale Arrays of Quantum Devices

June 16, 2025Job van Staveren; Luc Enthoven; Peter Luka Bavdaz; Marcel Meyer; Corentin Déprez; Ville NuutinenQuantum ComputingCryogenics, Demultiplexing, Electrodes, Electromagnetic heating, FinFETs, Logic gates, Program processors, Qubit, Voltage control, Wiring

Abstract: The rapidly growing number of qubits in semiconductor quantum computers requires a scalable control interface, including the efficient generation of dc bias voltages for gate electrodes. To avoid unrealistically complex wiring between any room-temperature electronics and the cryogenic qubits, this article presents an integrated cryogenic solution for the bias-voltage generation and distribution for large-scale […]

Memory-Optimized Cubic Splines for High-Fidelity Quantum Operations

May 28, 2025Jan Ole Ernst; Jan Snoeijs; Mitchell Peaks; Jochen WolfEnabling Technologies, UncategorizedCurve fitting, Field programmable gate arrays, Fitting, Hardware, Logic gates, Memory management, Polynomials, Quantum computing, Qubit, Splines (mathematics)

Abstract: Radio frequency pulses are preponderant for the control of quantum bits and the execution of operations in quantum computers. The ability to fine-tune key pulse parameters, such as time-dependent amplitude, phase, and frequency, is essential to achieve maximal gate fidelity and mitigate errors. As systems increase in scale, a larger proportion of the control […]

Q-Gen: A Parameterized Quantum Circuit Generator

May 20, 2025Yikai Mao; Shaswot Shresthamali; Masaaki KondoQuantum Software, UncategorizedComplexity theory, Computational modeling, Generators, Integrated circuit modeling, Logic gates, Quantum algorithm, Quantum circuit, Quantum computing, Quantum mechanics, Qubit

Abstract: Unlike most classical algorithms that take an input and give the solution directly as an output, quantum algorithms produce a quantum circuit that works as an indirect solution to computationally hard problems. In the full quantum computing workflow, most data processing remains in the classical domain except for running the quantum circuit in the […]

Analysis of Parameterized Quantum Circuits: On the Connection Between Expressibility and Types of Quantum Gates

May 19, 2025Yu Liu; Kazuya Kaneko; Kentaro Baba; Jumpei Koyama; Koichi Kimura; Naoyuki TakedaQuantum Computing, UncategorizedAccuracy, Additives, Computational modeling, Integrated circuit modeling, Kernel, Logic gates, Predictive models, Quantum circuit, Qubit, Topology

Abstract: Expressibility is a crucial factor of a parameterized quantum circuit (PQC). In the context of variational-quantum-algorithm-based quantum machine learning (QML), a QML model composed of a highly expressible PQC and a sufficient number of qubits is theoretically capable of approximating any arbitrary continuous function. While much research has explored the relationship between expressibility and […]