Layout Archives - IEEE Transactions on Quantum Engineering

Machine-Learning-Based Qubit Allocation for Error Reduction in Quantum Circuits

August 4, 2023Travis LeCompteQuantum Computing, UncategorizedIntegrated circuit reliability, Layout, Logic gates, Qubit, Reliability, Resource management, Routing

Quantum computing is a quickly growing field with great potential for future technology. Quantum computers in the current noisy intermediate-scale quantum (NISQ) era face two major limitations:1) qubit count and 2) error vulnerability. Although quantum error correction methods exist, they are not applicable to the current size of computers, requiring thousands of qubits, while current […]

Quantum Topology Optimization via Quantum Annealing

We present a quantum annealing-based solution method for topology optimization (TO). In particular, we consider TO in a more general setting, i.e., applied to structures of continuum domains where designs are represented as distributed functions, referred to as continuum TO problems. According to the problem’s properties and structure, we formulate appropriate subproblems that can be […]