Logic gates Archives - Page 2 of 13 - IEEE Transactions on Quantum Engineering

Feynman Meets Turing: Computability Aspects of Exact Circuit Synthesis, Gate Efficiency, and the Spectral Gap Conjecture

November 24, 2025Yannik N. Boeck, Holger Boche, Frank H.P. Fitzek,Quantum Computing6G mobile communication, Approximation algorithms, Circuit synthesis, Computational modeling, Hardware, Integrated circuit modeling, Logic gates, Quantum circuit, Quantum mechanics, Vectors

Abstract: We consider exact quantum circuit synthesis, quantum gate efficiency, and the spectral gap conjecture from the perspective of computable analysis. Circuit synthesis, in both its exact and its approximate variant, is fundamental to the circuit model of quantum computing. As an engineering problem, however, the practical and theoretical aspects of quantum circuit synthesis are […]

Hardware-Aware and Resource-Efficient Circuit Packing and Scheduling on Trapped-Ion Quantum Computers

November 14, 2025Miguel Palma, Shuwen Kan, Wenqi Wei, Juntao Chen, Kaixun Hua, Sara Mouradian, Ying MaoQuantum SoftwareCloud computing, Computer architecture, Computers, Hardware, Logic gates, Processor scheduling, Quantum circuit, Qubit, Resource management, Throughput

Abstract: The rapid expansion of quantum cloud services has led to long job queues due to single-tenant execution models that underutilize hardware resources. Quantum multiprogramming (QMP) mitigates this by executing multiple circuits in parallel on a single device, but existing methods target superconducting systems with limited connectivity, high crosstalk, and lower gate fidelity. Trapped-ion architecture, […]

Erasure-Tolerance Scheme for the Surface Codes on Neutral Atom Quantum Computers

October 31, 2025Fumiyoshi Kobayashi, Shota NagayamaQuantum ComputingAtom optics, Codes, Computers, Error analysis, Logic arrays, Logic gates, Measurement uncertainty, Optical arrays, Quantum computing, Qubit

Abstract: Neutral atom arrays manipulated with optical tweezers are promising candidates for fault-tolerant quantum computers due to their advantageous properties, such as scalability, long coherence times, and optical accessibility for communication. A significant challenge to overcome is the presence of non-Pauli errors, specifically erasure errors and leakage errors. Previous work has shown that leakage errors […]

Binary Tree Block Encoding of Classical Matrix

October 23, 2025Zexian Li, Xiao-Ming Zhang, Chunlin Yang, Guofeng ZhangQuantum ComputingBinary trees, Encoding, Logic gates, Measurement, Multiplexing, Protocols, Quantum circuit, Quantum state, Qubit, Sparse matrices

Abstract: State preparation and block encoding are essential subroutines in quantum computing. The former provides basic encoding of quantum states, while the latter transforms classical data into a matrix representation within a quantum circuit. Some quantum advantages are built on the assumption that the block-encoding subroutine has been compiled in the quantum circuit, and this […]

Exploration of Design Alternatives for Reducing Idle Time in Shor’s Algorithm: A Study on Monolithic and Distributed Quantum Systems

September 17, 2025Moritz Schmidt Abhoy Kole Leon Wichette Rolf Drechsler Frank Kirchner Elie MounzerQuantum Computing, UncategorizedArithmetic, Computer architecture, Hardware, Logic gates, Optimization, Quantum circuit, Quantum computing, Qubit, Registers, Standards

Abstract: Shor’s algorithm is one of the most prominent quantum algorithms, yet finding efficient implementations remains an active research challenge. While many approaches focus on low-level modular arithmetic optimizations, a broader perspective can provide additional opportunities for improvement. By adopting a midlevel abstraction, we analyze the algorithm as a sequence of computational tasks, enabling systematic […]

Benchmarking the Ability of a Controller to Execute Quantum Error Corrected Non-Clifford Circuits

September 9, 2025Yaniv Kurman Lior Ella Ramon Szmuk Oded Wertheim Benedikt Dorschner Sam StanwyckEnabling TechnologiesBenchmark testing, Circuits, Codes, Decoding, Fault tolerance, Fault tolerant systems, Logic gates, Measurement uncertainty, Quantum computing, Qubit

Abstract: Reaching fault-tolerant quantum computation relies on the successful implementation of non-Clifford circuits with quantum error correction (QEC). In QEC, quantum gates and measurements encode quantum information into an error-protected Hilbert space, while classical processing decodes the measurements into logical errors. QEC non-Clifford gates pose the greatest computation challenge from the classical controller’s perspective, as […]

A Grover-Meets-Simon Approach to Match Vector Boolean Functions

August 4, 2025Marco Venere; Alessandro Barenghi; Gerardo PelosiQuantum ComputingBenchmark testing, Boolean functions, Digital circuits, Integrated circuit interconnections, Libraries, Logic gates, Polynomials, Quantum algorithm, Time complexity, Vectors

Abstract: The Boolean matching problem via NP-equivalence requires determining whether two Boolean functions are equivalent or not up to a permutation and negation of the input binary variables. Its solution is a fundamental step in the electronic design automation (EDA) tool chains commonly used for digital circuit design. In fact, the library-mapping step of an […]

Simulation of Shor Algorithm for Discrete Logarithm Problems With Comprehensive Pairs of Modulo p and Order q

July 21, 2025Kaito Kishi; Junpei Yamaguchi; Tetsuya Izu; Noboru KunihiroQuantum InformationComputers, Cryptography, Fourier transforms, Logic gates, Noise measurement, Quantum algorithm, Quantum circuit, Quantum computing, Qubit, Registers

Abstract: The discrete logarithm problem (DLP) over finite fields, commonly used in classical cryptography, has no known polynomial-time algorithm on classical computers. However, Shor has provided its polynomial-time algorithm on quantum computers. Nevertheless, there are only few examples simulating quantum circuits that operate on general pairs of modulo p and order q. In this article, […]

SU(4) Gate Design via Unitary Process Tomography: Its Application to Cross-Resonance-Based Superconducting Quantum Devices

July 3, 2025Michihiko Sugawara; Takahiko SatohPhysical ImplementationsCalibration, Coherence time, Logic gates, Qubit, Resonance, Schedules, Superconducting microwave devices, Systematics, Tensors, Tomography

Abstract: In this article, we present a novel approach for implementing pulse-efficient SU(4) gates on cross resonance (CR)-based superconducting quantum devices. Our method introduces a parameterized unitary derived from the CR-Hamiltonian propagator, which accounts for ZZ-interactions. Leveraging the Weyl chamber’s geometric structure, we successfully realize a continuous two-qubit basis gate, RZZ(θ), as an echo-free pulse […]

Cryo-CMOS Bias-Voltage Generation and Demultiplexing at mK Temperatures for Large-Scale Arrays of Quantum Devices

June 16, 2025Job van Staveren; Luc Enthoven; Peter Luka Bavdaz; Marcel Meyer; Corentin Déprez; Ville NuutinenQuantum ComputingCryogenics, Demultiplexing, Electrodes, Electromagnetic heating, FinFETs, Logic gates, Program processors, Qubit, Voltage control, Wiring

Abstract: The rapidly growing number of qubits in semiconductor quantum computers requires a scalable control interface, including the efficient generation of dc bias voltages for gate electrodes. To avoid unrealistically complex wiring between any room-temperature electronics and the cryogenic qubits, this article presents an integrated cryogenic solution for the bias-voltage generation and distribution for large-scale […]